In a conventional personal computer system, as shown in FIG. 1, a core logic unit comprising a north bridge chip 11 and a south bridge chip 12 are used to control data flows among a microprocessor 10, a system memory 13, and a plurality of I/O devices including a graphics card 14. The microprocessor 10 accesses graphics data of the system memory 13 or outputs graphing commands to the graphics card 14 via the north bridge chip 11. The system memory 13 is generally a dynamic random access memory (DRAM) and comprises an AGP (Accelerated Graphics Port) memory block 131. The graphics card 14 is electrically connected to the north bridge chip 11 via an AGP bus, and comprises a graphics chip 141, a tile converter 143 and a local memory 142.
With the increasing demand of 3D graphing, the local memory 142 serves not only as a frame buffer but also as a texture buffer, a Z buffer and/or other graphics-related buffers to facilitate the improved 3D graphing functions. In order to comply with the 3D-graphing features and increase the processing speed of 3D graphics, the graphics data are stored and accessed in a so-called tile mode. However, before the graphics chip 141 stores the graphics data into the local memory 142, the graphics data are present in a linear mode. Therefore, the graphics data have to be converted into tile-mode graphics data by the tile converter 143 in advance, and then are stored in the local memory 142. As a result, the graphics data can be read and processed in a tile mode from the local memory 142 so as to enhance the data-processing speed of the graphics chip 141.
Furthermore, in addition to the local memory 142, the AGP memory block 131 of the system memory 13 is accessible by the graphics chip 141 via an AGP protocol when required. For a purpose of supporting data transmission in the tile mode, the linear-mode data stored in the AGP memory block 131 are also required to be rearranged into tile-mode data by way of software before being accessed by the graphics chip 141. As is understood, the processing speed of the system will be adversely affected by the transformation operation from a linear mode to a tile mode.